The plurality of memory cells is most commonly distributed over a memory area comprising M memory words each comprising N memory cells where M and N are integers and M*N is the size of the memory. Each of the memory cells of a same word also has a control input connected to a same word line and each of the same-ranking cells of each of the words has a data input connected to a same-ranking bit line and a complementary data input connected to a same-ranking complementary bit line.
The memory also has means not shown in the FIGURE, especially selection means to select a cell in the memory, and read means and write means for each memory cell.
The complexity of integrated circuits (the growing number of memory elements, the ever smaller surface area of each memory cell, etc.) goes together with a corresponding increase in the complexity of the manufacturing methods and the variability in the performance of integrated circuits, related to the manufacturing method, i.e. the variability in the performance of the integrated memories coming from a same silicon wafer or from a same batch of wafers.
The insertion of performance testing means into integrated circuits has therefore become a necessity in order to ensure that the circuits perform well and/or improve the performance of the manufacturing methods.
A prior-art testing method (known as the BIST for Built-In Self Test) consists in adding internal test circuits to the memory in order to test the performance of the memory cell. This technique generally has a non-negligible cost. It significantly increases the size (in terms of silicon surface area) of the integrated circuit memory and lowers its performance.